TSMC Roadmap of Next-generation Chipset
Recently, TSMC announced the roadmap of future advanced processes to the outside world at the 2022 Technology Symposium. According to the TSMC roadmap, 3nm (N3) will be mass-produced within this year, and as an iteration, 3nm will exist longer than the transitional 4nm, followed by N3E, N3P, and N3X.
TSMC first introduced N3’s FINFLEX, which includes 3-2 FIN, 2-2 FIN, and 2-1 FIN configurations with the following features:
- 3-2 FIN – Fastest clock frequency and highest performance for the most demanding computing needs.
- 2-2 FIN – Efficient Performance, a good balance of performance, power efficiency, and density.
- 2-1 FIN – Ultra-high power efficiency, lowest power consumption, lowest leakage, and highest density.
TSMC says FINFLEX extends the product performance, power efficiency, and density range of the 3nm family of semiconductor technologies, allowing chip designers to select the best option for each key functional block on the same chip using the same design toolset.
At the same time disclosed part of the 2nm (N2) information, the use of nanosheet transistors, to replace the use of years of FinFET. The so-called Nanosheet transistor, the industry generally believes should be TSMC’s version of GAAFET microstructure.
The N2 2nm process is 10-15% faster than the N3E at the same power consumption; 25-30% lower power consumption at the same speed. However, the N2 only increases chip density by about 10% compared to the N3E 3nm process.
The N2 process brings two important innovations: nanosheet transistors (called GAAFETs by TSMC) and backside power rails. The channels of GAA nanosheet transistors are surrounded by gates on all four sides to reduce leakage; in addition, their channels can be widened to increase drive current and improve performance, or shrunk to minimize power consumption and cost.
To provide sufficient power to these nanosheet transistors, TSMC’s N2 uses a backside power rail, which TSMC believes is one of the best solutions to combat resistance in the back-end-of-line (BEOL).
TSMC said that the N2 not only has a standard process for mobile processors but will also have an integrated solution for high-performance computing and small chips (Chiplet), which will be mass-produced in 2025.
