TSMC 3nm Process with 1.7x Higher Density Than 5nm, Also 20-30 Percent Less Power Uses

TSMC 3nm Process Technology

TSMC 3nm Process Technology

According to ItHome’s report, the China IC Design Industry 2021 Conference and Wuxi IC Industry Innovation Development Summit were held on December 22. Luo Zhenqiu, general manager of TSMC, gave a keynote speech titled “A New Era for the Semiconductor Industry”.

Mr. Luo announced that although many people say Moore’s Law is slowing down or fading away, TSMC is proving that Moore’s Law is still moving forward with new processes. TSMC’s 7nm process is launching in 2018, 5nm in 2020, 3nm in 2022 as scheduled, and 2nm is well under development.

According to TSMC’s roadmap, from 5nm to 3nm, transistor logic density can be increased by 1.7 times, performance can be increased by 11%, and power consumption can be reduced by 25%-30% with the same performance. How to achieve further miniaturization of transistors in the future, Luo Zhenqiu revealed two directions:

Change the structure of the transistor: Samsung will use a new GAA structure in the 3nm process, while TSMC 3nm still uses a fin-type field-effect transistor (FinFET) structure. However, TSMC has been developing the Nanosheet/Nanowire transistor structure (similar to GAA) for over 15 years and has achieved very solid performance.
Changing the material of transistors: two-dimensional materials can be used to make transistors. This will make the power consumption control better, and the performance will be stronger.

Luo Zhenqiu also said the future will use 3D packaging technology to improve the performance of the chip and reduce costs. Currently, TSMC has integrated advanced packaging-related technologies into the 3D Fabric platform.

In addition, TSMC will also be in the ADAS and intelligent digital cockpit automotive chip applications 5nm process platform “N5A”, which is expected to be launched in the third quarter of 2022, to meet the AEC-Q100, ISO26262, IATF16949, and other automotive process standards.

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