IBM and Samsung Announced VTFET Chip Design Technology
The current semiconductor process has developed to 5nm, next year Samsung TSMC is grabbing a 3nm process debut, after which there will be a 2nm process, and then after the 1nm node is a watershed moment, the need for whole new semiconductor technology.
According to Engadget, in San Francisco, California, IEDM 2021 International Electronic Components Conference, IBM, and Samsung jointly announced a chip design technology called Vertical Transport Field Effect Transistors (VTFET), the technology will be stacked vertically, and let the current also change to vertical flow, so that the number of transistors density again, but also significantly improve the efficiency of power use, and break through the current bottleneck in the 1nm process design.
Compared to the traditional design of stacking transistors horizontally, the vertical transmission of field-effect transistors will increase the density of transistor number stacking and increase the computing speed by two times, and also reduce power loss by 85% by allowing current to flow vertically (performance and endurance cannot be combined at the same time).
IBM and Samsung claim that the process could one day allow phones to be used for an entire week on a single charge. It could also make certain energy-intensive tasks, including encryption work, more power-efficient, they say, thereby reducing the environmental impact. IBM and Samsung have not yet revealed when they expect to apply the vertical transfer field-effect transistor design to actual products, but further news is expected soon.
