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IBM 2nm Chip Manufacturing Technology Officially Detailed

by Kamlesh Bhati
May 7, 2021
IBM 2nm Chip Manufacturing Technology
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IBM 2nm Chip Manufacturing Technology

Wafer development to today, many people want to know what comes after 5nm, the answer may be 4nm, or the more radical 2nm. Recently, the tech giant IBM released the world’s first 2nm chip manufacturing technology and has built the world’s first 2nm process of semiconductor chips.

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IBM 2nm Chip Manufacturing Technology

Compared with the mainstream 7nm chip, the same power consumption, 2nm chip computing speed to 45% faster, power consumption reduced by 75%. IBM said that the 2nm chip uses GAA (surround gate transistor) technology, transistor density (MTr/mm2, how many millions of transistors per square millimeter) is 333.33, almost twice as much as TSMC 5nm. And also higher than the outside world’s estimated TSMC 3nm process of 292.21 MTr/mm2.

IBM 2nm Chip Manufacturing Technology
Transistor Densities (Courtesy of Anandtech)

That is, within an area the size of a fingernail cover of 150 square millimeters, the 2nm chip technology can accommodate 50 billion transistors.

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  • IBM Research 2nm chip
    IBM Research 2nm: A close-up of a 2nm wafer fabricated at IBM Research’s Albany facility, with individual chips visible to the naked eye. (Courtesy of IBM)
  • IBM Research 2nm Wafer
    IBM Research 2nm Wafer: A 2nm wafer fabricated at IBM Research’s Albany facility. The wafer contains hundreds of individual chips. (Courtesy of IBM)
  • Row of IBM 2nm Chip nanosheet devices
    Row of 2nm nanosheet devices: 2 nm technology as seen using transmission electron microscopy. 2nm is smaller than the width of a single strand of human DNA. (Courtesy of IBM)
  • IBM 2nm Chip Manufacturing Technology
    IBM 2nm Chip Manufacturing Technology

IBM was also the first to build 7nm (2015) and 5nm (2017) chips, taking the lead in the definition of voltage and other indicators very early on. IBM 2nm Chip this time, the GAA (surround gate transistor) technology is used three layers. IBM introduced this as the first time the bottom dielectric isolation channel is used, it can achieve 12nm gate length, its internal spacing is the second generation of dry design, which helps the development of nanosheets. This is also the first time that the FEOL part of the process is exposed using EUV.

It should be noted that IBM does not have its fab, its manufacturing facility was sold to GEA in 2014, but the two signed a 10-year cooperation agreement, in addition, IBM also maintains cooperation with Samsung and Intel. Regarding GAA transistor technology, Samsung 3nm, Intel 5nm, and TSMC 2nm will be used for the first time.

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