ASML 1nm Lithography Machine Completed: Moore’s Law Not at End

ASML 1nm Lithography Technology

Moore’s Law to be extended beyond 1nm; IMEC and ASML to collaborate on the development of next-generation lithography technology

Mynavi

What is the endpoint of Moore’s Law? With the mass production of 5nm lithography and the breakthrough of 3nm, the end of Moore’s Law is becoming more and more elusive. What is certain is that as the process improves further, its cost increases exponentially.

According to reports from the Japanese media Mynavi, Luc Van den hove, CEO and President of IMEC, the European Microelectronics Research Center, said in an online presentation at a recent online event that progress has been made towards more advanced lithography in cooperation with ASML.

In the middle of this month, the ITF Forum was held in Tokyo, Japan. At the forum, IMEC, the Belgian semiconductor research organization that is working with ASML on the development of lithography, announced the technical details of the 3nm and below processes at the microscale level. At least for now, ASML has a clear roadmap for 3m, 2nm, 1.5nm, 1nm, and even Sub 1nm, and the 1nm era will see a significant increase in the size of the lithophones.

ASML has almost completed the design of the 1nm lithography machine.

Luc Van den hove, CEO and President of IMEC, gave the first keynote address, providing an overview of the company’s research and emphasizing the commercialization of the next generation of high-resolution EUV lithography, high-NA EUV lithography, through close collaboration with ASML. IMEC Inc. It was emphasized that the process of downsizing to 1nm and below would continue.

Many semiconductor companies, including Japan, have withdrawn from process miniaturization, claiming that Moore’s Law has come to an end, or that it is too costly and unprofitable. While many lithography tool manufacturers in Japan have withdrawn from the EUV lithography development phase, semiconductor research institutions IMEC and ASML have been collaborating on the development of EUV lithography, which is critical for ultra-fine scales.

IMEC Announces Roadmap for Logic Devices Down to 1nm and Beyond

IMEC will present a roadmap for the miniaturization of logic devices at 3nm, 2nm, 1.5nm and below 1nm at ITF Japan 2020.

IMEC’s roadmap for logic device miniaturization

The PP is the pitch (nm) for polysilicon interconnects and the MP is the pitch (nm) for fine metal wiring under the name of the upstream technology node. It should be noted that in the past technology nodes referred to minimum process dimensions or gate lengths, but now they are just “labels” and do not refer to the physical length of a location.

The structures and materials described here, such as BPR, CFET, and channels using 2D materials, have been published separately.

High NA of EUVs is essential for further miniaturization

According to TSMC and Samsung Electronics, starting with the 7nm process, some processes have introduced EUV lithography equipment with NA=0.33, and the 5nm process has also achieved an increase in frequency, but for ultra-fine processes after 2nm, higher resolution and higher lithography equipment NA (NA=0.55) need to be achieved.

The technology roadmap of EUV lithography system for process miniaturization of logic devices.

According to IMEC, ASML has completed the basic design as a high-NA EUV exposure system for the NXE:5000 series, but commercialization is planned for around 2022. This next-generation system will be very tall due to its huge optics, most likely under the ceiling of a conventional cleanroom.

Current EUV lithography system (NA=0.33) (front) compared to the next generation of high NA EUV lithography system (NA=0.55) (back).

ASML has been working closely with IMEC in the past to develop lithography technology, but to develop lithography processes using high NA EUV lithography tools, a new “IMEC-ASML High NA EUV Lab” has been established on the IMEC campus to facilitate joint research and development of lithography processes using high NA EUV lithography process for tools. The company also plans to work with material suppliers to develop masks and resists.

IMEC-ASML High NA EUV Laboratory

In addition to these four goals, as miniaturization moves to 3nm, 2nm, 1.5nm, and even beyond 1nm to sub-1nm, we will strive to achieve the following Microprocessors that are environmentally friendly and suitable for a sustainable society. He showed great enthusiasm to continue his commitment to process miniaturization.

Emphasizing PPAC-E, he added E (environmental) process miniaturization to the traditional PPAC.

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